1. Field of the Invention
This invention relates to packaging for integrated circuits and, more particularly, to chip-scale packaging.
2. Prior Art
While many packaging schemes for integrated-circuit use packages which are much larger in volume than an integrated-circuit die, chip-scale packaging techniques provide integrated-circuit packages which are closer in size, or scale, to the integrated-circuit die. Some current chip-scale packaging techniques use a relatively thick laminated substrate, such as an epoxy board, or else a polyimide film substrate and fix the integrated-circuit die to the substrate using flip-chip, leadless packages to attach the integrated-circuit die to the substrate with solder bumps
For flip-chip, chip-scale packages with either laminated substrates or with polyimide substrates, it is expensive to provide high-density conductors on such substrates.
Flip-chip, chip-scale packages with either laminated substrates have reliability problems because of the mismatch between the thermal coefficients of expansion (TCE) of an organic substrate (17 ppm/.degree. C.) and a silicon die (7 ppm/.degree. C.). The differences in TCEs within current chip-scale, flip-chip packages cause reliability problems due to cracking of the solder bump connections between the integrated-circuit chips and the organic substrates. Currently, an underfill layer of epoxy material can be located in the space between the lower part of the flip-chip die and the upper surface of the laminated organic substrate in an attempt to improve solder joint reliability, but underfill itself can cause die cracking and delamination.
For a flip-chip, chip-scale package with a conventional one-or-two layer ceramic substrate, it is relatively inexpensive to provide densely packed conductors. The ceramic material has a TCE of 7 ppm/.degree. C. and the reliability of a flip-chip package with a ceramic substrate is well established. However, because of the brittleness of the ceramic substrate material, the thickness of the ceramic substrate has to be at least 0.65 mm to prevent the substrate from cracking during handling. A ceramic substrate for a flip-chip package therefore has to be on the order of 0.65 mm thick. This results in the thickness of the overall ceramic, flip-chip package being much greater than is desired for miniature applications.
Although the area of a chip scale package is quite small, the reliability of chip-scale packages is still questionable due to the thermal expansion mismatch between the substrate (7 ppm/.degree. C.) and the organic board (17 ppm/.degree. C.).
Currently, no low-cost, very small form factor chip scale package is available in industry.
FIG. 1 illustrates a typical prior art chip-scale package 10 configuration . A silicon flip-chip die 12 is mounted to the top surface of a laminated organic substrate 14 , such as an epoxy circuit board. A number of solder bumps, typically shown as 16, are heated to form solder bonds between respective solder-bump mounting pads on the surface of the flip-chip die 12 and on the top surface of the thick organic laminated substrate 14. The thick organic laminated epoxy substrate 14 typically has a thickness of 1.0 mm. An underfill layer 18 of epoxy material is located in the space between the lower part of the flip-chip die 12 and the upper surface of the laminated organic substrate 14. The underfill layer 18 is formed with a layer of liquid epoxy material which is drawn into the space between the die and the substrate by capillary action and cured. The underfill layer 18 reinforces the solder bump 14 to help prevent failure of the solder joints caused by the differences between the TCEs of the die 12 and the organic substrate 14.
To attach the package 10 to a mounting surface , a number of solder balls, typically shown as 20, are heated to provide respective connections between solder ball mounting pads on the bottom surface of the organic laminated substrate 14 and solder ball mounting pads on the mounting surface of, for example, a printed circuit board.
As mentioned previously, it is expensive to provide a high-density set of conductors on a laminated epoxy substrates.
FIG. 2 shows another typical prior art chip-scale package 30 configuration. This configuration is similar to that of FIG. 1. except for the use of a more inexpensive but still relatively thick ceramic substrate. A silicon flip-chip die 32 is mounted to the top surface of a ceramic substrate 34. Solder bumps, typically shown as 36, are heated to form solder bonds between respective solder-bump mounting pads on the surface of the flipchip die 32 and on the top surface of the thick ceramic substrate 34, which typically has a thickness of at least 0.65 mm. An underfill layer 38 of epoxy material is located in the space between the lower part of the flip-chip die 32 and the upper surface of the ceramic substrate 34 and is also formed with a layer of liquid epoxy material being drawn into the space between the die 32 and the substrate 34 by capillary action and cured. The underfill layer 38 similarly reinforces the solder bump 34 joints to prevent failure of the solder joints by cracking caused by the differences in temperature between the die 32 and the substrate 34.
The package 30 is attached to a mounting surface with a number of solder balls, typically shown as 40, which are heated to provide respective connections between solder ball mounting pads on the bottom surface of the ceramic substrate 34 and solder ball mounting pads on the mounting surface of, for example, a printed circuit board.
As mentioned previously, for a conventional one-or-two layer ceramic substrate, it is relatively inexpensive to provide densely packed conductors for a flip-chip chip-scale package. The reliability of a flip-chip package with a thick ceramic substrate is also well established. However, a ceramic substrate is relatively brittle and the thickness of the substrate has to be at least 0.65 mm to prevent the substrate from cracking during handling. This results in the overall thickness of the ceramic, flip-chip package being much greater than is desired.
Consequently a need exists for a low-cost, chip-scale ceramic package which can use a ceramic substrate with a very small form factor but still provide good reliability.